1. Field of the Invention
The present invention relates to the manufacture of a semiconductor device and, in particular, to a method for forming a planar insulation film on an uneven surface of a substrate on which elements and interconnections are formed.
2. Description of the Prior Art
With increasing semiconductor device density, the down scaling of transistors and metal interconnections is accelerated, and further demands are placed on multilayer structures. However, it is difficult for conventional manufacturing method using lithography technology to appropriately form a fine and multilayered interconnection structure. The reason is that the resolution required to miniaturize interconnection patterns is close to the limit of current lithography technology and the multilayering of interconnections generates an uneven surface which prevents forming fine patterns thereon.
A planarization process for removing steps from the surface of semiconductor devices in a multilayered structure has been proposed as a solution for the above-mentioned problem. For example, in the paper "A Highly Reliable Multilevel Interconnection Process for 0.6 .mu.m CMOS Devices" (IEEE, Jun. 11-12, 1991, VMIC Conference, pp. 13 to 19), a multilayered interconnection structure can be formed using a planarization process based on Atmospheric Pressure Chemical Vapor Deposition (APCVD) using ozone and tetraethoxysilane (TEOS).
FIGS. 1A to 1D show a manufacturing method of a semiconductor device using a conventional planarization process. As shown in FIG. 1A, metal interconnection 1 is first formed on a semiconductor substrate 2 using lithography and dry etching methods. As shown in FIG. 1B, a silicon oxide film 3 is then deposited on both the interconnection sections and other surface of the substrate 2 using plasma CVD. As shown in FIG. 1C, a silicon oxide film 6 is deposited on the surface by means of APCVD using ozone and TEOS. Furthermore, as shown in FIG. 1D, the silicon oxide film 6 is dry-etched to form a silicon oxide film 6'. After dry-etching, a silicon oxide film 13 is formed on the exposed silicon oxide film 6' using plasma CVD. On the silicon oxide film 13, another interconnection for a second layer is formed in the same manner to form a multilayered structure.
However, such a conventional manufacturing method has the following disadvantages:
1) The method is complicated and requires many manufacturing steps;
2) It is virtually impossible to avoid differences in levels between a surface with interconnections having a large interval and other surface with interconnections having a small interval; and
3) Even after the planarization process, significant steps remain on the surface and the step amount increases with the number of layers formed.
Therefore, conventional methods can only produce a multilayered structure with a small number of layers.